The integrated circuit (IC) industry is continually striving to manufacture metallic interconnect structures which have improved reliability and performance. FIG. 1 illustrates an interconnect structure which has been utilized in the prior art. In FIG. 1, a titanium (Ti) layer 20 is first deposited. After formation of the titanium (Ti) layer 20, a titanium nitride (TiN) layer 22 is then formed on top of the layer 20. The bulk of the metallic interconnect is then formed overlying the layer 22 by depositing a thick aluminum or aluminum alloy (Al) layer 24. On top of this thick aluminum (Al) layer 24 is deposited a thin titanium nitride (TiN) layer 26 which is utilized as an anti-reflective coating (ARC) layer for the prior art structure.
Typically, the interconnect of FIG. 1 is covered with a dielectric layer (not illustrated in FIG. 1) which is then photo-lithographically patterned and etched to form via/contact openings (not illustrated in FIG. 1) through the dielectric layer. These via/contact openings will expose layer 26, reactive ion etch (RIE) through the layer 26, and expose a top contact portion of the aluminum (Al) layer 24. These via/contact openings typically have high aspect ratios wherein the diameter of these via/contact openings will typically be less than 0.8 microns and the depth of these vias/contacts may be greater than 1.0 micron. Due to the fact that the aluminum layer 24 has now been exposed by the RIE process, additional barrier layers must now be deposited to protect the aluminum layer 24 in FIG. 1 from subsequent tungsten deposition processing. In the prior art process of FIG. 1, the via/contact opening is coated with titanium (Ti) and then titanium nitride (TiN). As is known in the art, deposition of these materials into high aspect ratio contacts is complicated and problematic. The proper amount of protective barrier material is not always formed at the bottom of via/contact openings. This problem is only exacerbated as aspect ratio of contacts and vias continue to increase. Therefore, the need exists for a process wherein subsequently deposited barrier layers within large aspect ratio via/contacts are no longer needed.
Due to the barrier limitations of FIG. 1, the IC industry began to use an interconnect metallic structure as illustrated in FIG. 2. FIG. 2 illustrates that a thick aluminum (Al), or aluminum alloy layer 28 is first formed. A titanium (Ti) layer 30 is then deposited over a top of the layer 28. It is important to note that a titanium aluminide (Al.sub.3 Ti) is formed at the interface between the titanium layer 30 and the aluminum layer 28 of FIG. 2 after an anneal step. This Al.sub.3 Ti layer is disadvantageous because copper (Cu), which is typically used to form an aluminum-copper (Al--Cu) alloy as the aluminum layer 28 to improve in electromigration reliability, will diffuse along the Al.sub.3 Ti interface resulting in reduced electromigration reliability for the aluminum in the layer 28. After formation of the titanium (Ti) layer 30 in FIG. 2, a titanium nitride (TiN) layer 32 is deposited over the layer 30.
In a manner similar to FIG. 1, a dielectric layer is then deposited over the structure of FIG. 2 and via/contact openings are etched to expose the layer 32 of FIG. 2. It is important to note that the etch chemistries used to expose the layer 32 may etch through the layer 32 thereby exposing the titanium (Ti) layer 30 of FIG. 2. If the titanium layer 30 is exposed, subsequent tungsten (W) processing which utilizes tungsten fluoride (WF.sub.6) will result in an adverse reaction of the titanium layer 30 due to presence of fluorine. Therefore, the inclusion of titanium near the surfaces of any interconnect structure is not advantageous when tungsten fluoride processing is utilized to form W plugs. Therefore, a need exists for an interconnect process which reduces or eliminates the presence of titanium (Ti) in the final interconnect structure and reduces or eliminates the formation of electromigration-degrading Al.sub.3 Ti within the interconnect structure.
FIG. 3 illustrates yet another interconnect structure which may be used in the integrated circuit (IC) industry. FIG. 3 illustrates a structure which begins by depositing an aluminum or aluminum alloy layer 34. A titanium nitride (TiN) layer 36 is then deposited over the aluminum (Al) layer 34. It is important to note that in the formation of the titanium nitride (TiN) layer 36, nitrogen will react with the aluminum layer 34 to form a thin, and highly resistive, aluminum nitride (AlN) layer between the titanium nitride layer 36 and the aluminum layer 34. The thin and highly resistive aluminum nitride (AlN) layer between the layers 34 and 36 will adversely affect via/contact resistance of the structure of FIG. 3. Therefore, the formation of aluminum nitride (AlN) within an interconnect structure is disadvantageous and should be avoided in semiconductor interconnect technology. After formation of the layer 36, a thick titanium (Ti) layer 38 is deposited. Over a top of the titanium layer 38 is deposited a titanium nitride (TiN) layer 40. It is important to note that the WF.sub.6 processing that is used to form tungsten (W) plugs above the structure of FIG. 3 is also disadvantageous in a manner similar to that discussed previously for FIG. 2 due to the large presence of unreacted titanium (Ti) in layer 38. Therefore, AlN and large areas of unreacted Ti should be avoided in interconnect structures if possible.
In addition to the prior art illustrated in FIGS. 1-3, it is generally known that it is disadvantageous in the IC industry to utilize titanium nitride (TiN) targets to perform sputtering of titanium nitride layers in interconnect structures. Titanium nitride targets result in severe particulate problems within processing chambers, and the Ti to N ratio varies throughout a titanium nitride (TiN) target whereby subsequently deposited TiN layers suffer from nitrogen concentration variations. Therefore, newer generations of interconnect structures should avoid the use of a titanium nitride (TiN) sputter target in sputtering or deposition chambers.
Generally, the devices of FIGS. 1-3, utilize multiple chambers (e.g. some use three or four processing chambers) in order to form a single composite interconnect layer. It is well known that the fewer chambers which are utilized in processing results in a decrease in material defectivity. Therefore, it is possible to increase IC yield by reducing the number of chambers through which interconnect structures must be processed. Furthermore, if fewer wafer chambers can be used and no shutters or dummy wafers need to be utilized, then the throughput of the interconnect deposition system can be improved in the manufacture of an interconnect structure for a semiconductor device. Improved throughput reduces cost, improves cycle time and is always advantageous in the integrated circuit industry.
In addition, while the devices of FIGS. 1-3 are adequate in terms of electromigration, the electromigration reliability of the devices of FIGS. 1-3 are marginal by today's standards and may be approaching theoretical limits. Therefore, the need for an interconnect structure which has improved electromigration reliability is desired. Furthermore, any interconnect structure which can reduce wafer stress and reduce via/contact resistance is also advantageous in the IC arts.
Therefore, the need exists in the IC art for an interconnect structure which accomplishes one or more of the following: (1) eliminate the need for barriers deposited within high aspect ratio contacts/vias; (2) avoid the need for a composite titanium nitride (TiN) sputter targets; (3) reduce or eliminate titanium material in the interconnect structure for more compatibility with tungsten WF.sub.6 processing; (4) reduce or eliminate aluminum nitride (AlN) formation to reduce resistivity and improve via/contact resistance; (5) reduce or eliminate titanium aluminide (Al.sub.3 Ti) formation to reduce film stress; (6) improve overall electromigration reliability; (7) increase the throughput of deposition/sputtering systems; and (8) improve yield due to reduced wafer handling.